Title :
Bit error rate analysis in Charge Trapping memories for SSD applications
Author :
Grossi, Alessandro ; Zambelli, Cristian ; Olivo, Piero
Author_Institution :
Dipt. di Ing., Univ. di Ferrara, Ferrara, Italy
Abstract :
Different program algorithms are experimentally characterized on CT-NAND Flash Arrays at 4X technology node. The advantages in terms of endurance, retention and read disturb reduction obtained with the proposed algorithms are shown. The positive effects of these algorithms can be increased using an error-reduction procedure called Read Retry, making feasible the usage of CT-NAND memories in MLC-SSD applications.
Keywords :
NAND circuits; driver circuits; error statistics; flash memories; 4X technology node; CT-NAND flash array; CT-NAND memory; MLC-SSD application; bit error rate analysis; charge trapping memory; error-reduction procedure; program algorithm; read retry; solid state drive; Ash; Bit error rate; Computer architecture; Electron traps; Error correction codes; Microprocessors; Programming; BER; CT-NAND flash; MLC; SLC; SSD; bit error rate; multi level cell; single level cell; solid state drive;
Conference_Titel :
Reliability Physics Symposium, 2014 IEEE International
Conference_Location :
Waikoloa, HI
DOI :
10.1109/IRPS.2014.6861161
