Title :
Preventing single event latchup with deep P-well on P-substrate
Author :
Uemura, Toshifumi ; Kato, Toshihiko ; Tanabe, Ryo ; Iwata, Hiroshi ; Matsuyama, Hiroki ; Hashimoto, Mime ; Takahisa, K. ; Fukuda, Motohisa ; Hatanaka, Katsumori
Author_Institution :
Fujitsu Semicond. Ltd., Tokyo, Japan
Abstract :
We propose a method that prevents single event latchup (SEL) using deep P-well on P-substrate. To confirm the effectiveness of the proposed method, SEL and single event upset (SEU) are evaluated for three well configurations; double-well, ordinary triple-well and the proposed deep P-well on P-substrate. Neutron irradiation test shows that the proposed method achieves SEL prevention without SEU increase.
Keywords :
SRAM chips; radiation hardening (electronics); P-substrate; SEL prevention; SEU; deep P-well configurations; double-well configurations; neutron irradiation test; ordinary triple-well configurations; single event latchup; single event upset; Bipolar transistors; CMOS integrated circuits; Neutrons; Radiation effects; Random access memory; Reliability; Single event upsets; Deep-well; Double-well; Latchup; Neutorn; SRAM; Single Event; Single Event Latchup (SEL); Soft-error; Terrestial environment; Triple-well;
Conference_Titel :
Reliability Physics Symposium, 2014 IEEE International
Conference_Location :
Waikoloa, HI
DOI :
10.1109/IRPS.2014.6861175
