Title :
Utilizing device stacking for area efficient hardened SOI flip-flop designs
Author :
Kauppila, J.S. ; Loveless, T.D. ; Quinn, R.C. ; Maharrey, J.A. ; Alles, Michael L. ; McCurdy, Michael W. ; Reed, R.A. ; Bhuva, B.L. ; Massengill, Lloyd W. ; Lilja, K.
Author_Institution :
Vanderbilt Univ., Nashville, TN, USA
Abstract :
D-flip-flop designs hardened with stacked transistors for a 32-nm SOI CMOS technology show greater than three orders of magnitude decrease in soft error cross-section, up to a heavy-ion tested tilt angle of 55°, and greater than one order of magnitude decrease in cross-section for a heavy-ion tested tilt angle of 75° with less than 50% area penalty compared to unhardened D-flip-flop designs.
Keywords :
CMOS logic circuits; flip-flops; integrated circuit design; radiation hardening (electronics); silicon-on-insulator; three-dimensional integrated circuits; CMOS technology; D-flip-flop; area efficient hardened SOI flip-flop design; complementary metal oxide semiconductor; device stacking; heavy-ion tested tilt angle; magnitude decrease; silicon-on-insulator; size 32 nm; soft error cross-section; stacked transistor; Flip-flops; Inverters; Ions; Logic gates; Standards; Testing; Transistors; CMOS; Hardened By Design; SOI; Soft Errors;
Conference_Titel :
Reliability Physics Symposium, 2014 IEEE International
Conference_Location :
Waikoloa, HI
DOI :
10.1109/IRPS.2014.6861176
