A new faster method for calculating the resolution coefficient of cmos latches: design of an optimum latch

Author

Bellido, M.J. ; Valencia, Manuel ; Acosta, Antonio J. ; Barriga, Angel ; Huertas, Jose Luis ; Dominguez-Castro, R.

Author_Institution

Cenlro Nacional de Microclectronica

fYear

1993

fDate

3-6 May 1993

Firstpage

2019

Lastpage

2022

Keywords

Circuit simulation; Fabrication; Geometry; Latches; Logic; Metastasis; Process design; Routing; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

IEEE

Print_ISBN

0-7803-1281-3

Type

Filename

693075

Link To Document