DocumentCode :
1878195
Title :
Reducing losses in multilevel coupled inductor inverters using interleaved discontinuous SVPWM
Author :
Vafakhah, Behzad ; Knight, Andy ; Salmon, John
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB, Canada
fYear :
2010
fDate :
21-25 Feb. 2010
Firstpage :
2013
Lastpage :
2020
Abstract :
This paper presents generalized interleaved Discontinuous Space Vector PWM (DSVPWM) schemes for 3-level 3-phase 6-switch split-wound Coupled Inductor Inverters (CII). A simplified approach is applied to the generation of interleaved DSVPWM schemes with the need to minimize high frequency current ripple and associated losses in the coupled inductor and the inverter. The performance of the CII is investigated and compared for DSVPWM schemes. The current ripple is analyzed based on the position of the discontinuous period for several DSVPWM schemes with different loads and power factors. Regardless of the loads, 60° discontinuous SVPWM around the positive and negative peaks of the fundamental reference voltage, DSVPWM1, lowers losses in the coupled inductor. The simulation and experimental results validate the drive performance.
Keywords :
PWM invertors; power inductors; 3-level 3-phase 6-switch split-wound coupled inductor inverters; generalized interleaved Discontinuous Space Vector PWM scheme; high frequency current ripple minimization; interleaved discontinuous SVPWM; loss reduction; multilevel coupled inductor inverters; power factors; Frequency; Inductance; Inductors; Leg; Performance loss; Pulse width modulation inverters; Space vector pulse width modulation; Switches; Topology; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Applied Power Electronics Conference and Exposition (APEC), 2010 Twenty-Fifth Annual IEEE
Conference_Location :
Palm Springs, CA
ISSN :
1048-2334
Print_ISBN :
978-1-4244-4782-4
Electronic_ISBN :
1048-2334
Type :
conf
DOI :
10.1109/APEC.2010.5433511
Filename :
5433511
Link To Document :
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