A Reconfigurable Processing Unit for Digital Circuit Testing using Built-In Self-Test Techniques

This paper introduces a novel architecture that is targeted for digital circuit testing application by means of built-in self-test techniques. These applications consist of static configurable hardware designs that will execute the testing of the digital circuit in hardware, where previous literature has established it´s testing in software consequently introducing a hardware accelerator. In this paper we show the novel architecture to digital circuit testing in hardware on a reconfigurable processing unit for compile-time reconfiguration