Title :
Statistical Characterization of Partially-Depleted SOI Gates
Author :
Kim, Kyung Ki ; Kim, Yong-Bin ; Park, N. ; Lombardi, F.
Author_Institution :
Dept. of Electron. & Comput. Eng., Northeastern Univ., Boston, MA
Abstract :
This paper presents a novel statistical characterization methodology for accurate timing analysis for partially depleted silicon-on-insulator (PD-SOI) digital circuits. The proposed methodology is applied to ISCAS85 benchmarks circuits, and the results show that the error is within 5% comparing to HSpice simulation results
Keywords :
digital integrated circuits; integrated circuit design; silicon-on-insulator; statistical analysis; digital circuits; partially-depleted SOI gates; silicon-on-insulator; statistical analysis; statistical characterization; timing analysis; Circuit simulation; Delay effects; Digital circuits; History; MOSFET circuits; Propagation delay; Silicon on insulator technology; Statistical analysis; Timing; Uncertainty; Cell Characterization; SOI (Silicon on Insulator); Statistical Analysis; Statistical Modeling; Timing Analysis;
Conference_Titel :
Instrumentation and Measurement Technology Conference, 2006. IMTC 2006. Proceedings of the IEEE
Conference_Location :
Sorrento
Print_ISBN :
0-7803-9359-7
Electronic_ISBN :
1091-5281
DOI :
10.1109/IMTC.2006.328407
