Influence of STI stress on leakage current in buried P-N junction

Reduction of leakage current is a grand challenge in logic and analog devices from viewpoints of low power consumption, high resolution, low noise, and so on. As for the P-N junction leakage current, it is reported that the leakage current is caused by several factors such as junction depth [1], shallow trench isolation (STI) stress [2], metal contamination, and crystal defects [3]. In this paper, we focused on the influence of the STI stress on the junction leakage current. To clarify the impact of internal stress in the silicon substrates on the leakage current, a buried P-N junction was used. The buried P-N junction has less sensitivity to SiO₂/Si interface states which could dominate the leakage current, and is applied to low leakage devices. We quantified the magnitude of the mechanical stress utilizing Raman spectroscopy and examined the process parameter to reduce the leakage current.