Title :
An FPGA implementation of a flexible architecture for H.263 video coding
Author :
Garrido, M.J. ; Sanz, C. ; Jimenez, M. ; Meneses, J.M.
Author_Institution :
Univ. Politecnica de Madrid, Spain
Abstract :
In this paper the implementation of an H.263 base-line video coder on an FPGA-based platform is explained. The coder consists of a set of specialised processors for the main tasks (DCT, quantizations, motion estimation) and a RISC for the scheduling tasks. The design has been written in synthesizable Verilog and fully tested with hardware-software co-simulation using standard video sequences. Finally, the coder has been tested on a prototyping board with a RISC processor and an FPGA.
Keywords :
discrete cosine transforms; field programmable gate arrays; motion estimation; processor scheduling; reduced instruction set computing; transform coding; video codecs; video coding; DCT; FPGA; H.263; RISC; base-line video coder; flexible architecture; hardware software co-simulation; motion estimation; prototyping board; quantizations; scheduling tasks; specialised processors; standard video sequences; synthesizable Verilog; testing; video coding; Discrete cosine transforms; Field programmable gate arrays; Hardware design languages; Motion estimation; Processor scheduling; Quantization; Reduced instruction set computing; Testing; Video coding; Video sequences;
Conference_Titel :
Consumer Electronics, 2002. ICCE. 2002 Digest of Technical Papers. International Conference on
Conference_Location :
Los Angeles, CA, USA
Print_ISBN :
0-7803-7300-6
DOI :
10.1109/ICCE.2002.1014027
