Analysis of increased parallelism in FPGA implementation of neural networks for environment/noise classification and removal

In this paper, we give baseline architecture¹ for a system of neural networks, for the tasks of feature extraction, environment/noise classification and modeling, on FPGA (Field Programmable Gate Array) and also gives a methodology of studying and analyzing the implementation of such ISP (Intelligent Signal Processing) algorithms As one of the major benefits of neural networks is its parallel structure for computation, we introduce parallelism in varying degrees, in our implementation method and give an analysis of the designs in terms of hardware utilization and time for computation, for all three networks. We then conclude with the best configuration in terms of number of neurons computed per computing unit², for all three networks. This experiment will provide baseline architecture and analysis results for hardware implementation of a set of ISP tasks. The designs have been implemented on FPGA with Verilog and tested with MATLAB results as reference, for particular examples in each task.