Fault modeling for physical failures for CMOS circuits

Author

Zaghloul, M.E. ; Gobovic, D.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., George Washington Univ., DC, USA

fYear

1988

fDate

7-9 June 1988

Firstpage

677

Abstract

The authors propose a fault simulation model for CMOS VLSI circuits which can handle physical faults as gate-to-drain/source shorts. A relation is established between the inverse voltage of a fault-free inverter and the faulty output voltage of a faulty inverter. This relation is then used to study the propagation of the faulty signal through a successive gate.<>

Keywords

CMOS integrated circuits; VLSI; circuit reliability; digital simulation; failure analysis; integrated logic circuits; logic gates; logic testing; CMOS VLSI circuits; CMOS circuits; fault modeling; fault simulation model; fault-free inverter; faulty inverter; faulty output voltage; faulty signal propagation; inverse voltage; physical failures; physical faults; shorts; Circuit faults; Circuit simulation; Failure analysis; Inverters; MOS devices; SPICE; Semiconductor device modeling; Switches; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo, Finland

Type

conf

DOI

10.1109/ISCAS.1988.15016

Filename

15016

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1879091