Design of speed, energy and power efficient reversible logic based vedic ALU for digital processors

Now days most of the circuits which are going to be designed to perform any specific or safety critical operations are mainly based upon the digital domain, where microprocessors and microcontrollers plays an important role to design these digital circuits. ALU is the heart of these processors. By optimizing this co-processor a highly efficient digital processor can be obtained. So this paper is totally devoted to design speed, energy and power efficient Arithmetic Logic Unit. Speed of ALU is greatly depends upon the speed of multiplication unit. There are so many multiplication techniques have been devised at algorithmic and structural level. After a thorough study and deep analysis we have found that Vedic Urdhva Triyambakam multiplication algorithm is the best algorithm as it generates partial products in the parallel manner. In this paper we have proposed a new tree multiplication structure based architecture to design this Vedic multiplier. To generate partially generated products divide and conquer approach has been used. For the addition of partially generated products a new addition tree structure has been proposed. It provides better speed in comparison Array, Booth, Wallace, Modified Booth Wallace, Karatsuba and Vedic Karatsuba Multiplier as well as it is faster than Vedic multiplier which has been proposed by L. Shriraman [2], and Devika Jaina [3]. To make ALU energy and power efficient, a new reversible logic gate has been proposed which is similar to Fredkin Gate [18]. After integrating these modules we have obtained the speed, energy and power efficient ALU. The proposed Arithmetic Logic Unit is coded in Verilog HDL, synthesized and simulated using Xilinx ISE 9.2i software.