Title :
A high performance lattice architecture of 2D discrete wavelet transform for hierarchical image compression
Author :
Taegeun Park ; Sunkyung Jung
Author_Institution :
Comput. & Electron. Eng., Catholic Univ. of Korea, Bucheon, South Korea
Abstract :
This paper presents a high performance lattice architecture of 2D discrete wavelet transform (DWT), which is scalable to extend to an arbitrary 2D DWT with M taps and J levels. The proposed lattice structure fits in a VLSI implementation due to its regularity and shows the period of N/sup 2//2 to compute an N/spl times/N image because the even and odd rows are processed simultaneously.
Keywords :
VLSI; code standards; data compression; discrete wavelet transforms; image coding; transform coding; 2D DWT; JPEG2000; MPEG4; VLSI implementation; discrete wavelet transform; hierarchical image compression; high performance lattice architecture; scalable transform; Computer architecture; Delay; Digital-to-frequency converters; Discrete wavelet transforms; Filters; Hardware; Image coding; Lattices; Processor scheduling; Very large scale integration;
Conference_Titel :
Consumer Electronics, 2002. ICCE. 2002 Digest of Technical Papers. International Conference on
Conference_Location :
Los Angeles, CA, USA
Print_ISBN :
0-7803-7300-6
DOI :
10.1109/ICCE.2002.1014062
