Compact implementation of SHA3-512 on FPGA

Author

Arshad, Abida ; Kundi, Dur-e-Shahwar ; Aziz, Ahmedullah

Author_Institution

Dept. of Electr. Eng., Nat. Univ. of Sci. & Technol., Islamabad, Pakistan

fYear

2014

fDate

12-13 June 2014

Firstpage

29

Lastpage

33

Abstract

In this work we present a compact design of newly selected Secure Hash Algorithm (SHA-3) on Xilinx Field Programable Gate Array (FPGA) device Virtex-5. The design is logically optimized for area efficiency by merging Rho, Pi and Chi steps of algorithm into single step. By logically merging these three steps we save 16 % logical resources for overall implementation. It in turn reduced latency and enhanced maximum operating frequency of design. It utilizes only 240 Slices and has frequency of 301.02 MHz. Comparing the results of our design with the previously reported FPGA implementations of SHA3-512, our design shows the best throughput per slice (TPS) ratio of 30.1.

Keywords

cryptography; field programmable gate arrays; logic design; Chi step; FPGA; Pi step; Rho step; SHA3-512; TPS; Virtex-5; Xilinx field programable gate array device; area efficiency; compact implementation; cryptographic hash function; latency reduction; maximum operating frequency enhancement; secure hash algorithm; throughput-per-slice ratio; Algorithm design and analysis; Arrays; Clocks; Field programmable gate arrays; Hardware; Signal processing algorithms; Throughput; Cryptography; FPGA; SHA3; Security; Xilinx;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Assurance and Cyber Security (CIACS), 2014 Conference on

Conference_Location

Rawalpindi

Print_ISBN

978-1-4799-5851-1

Type

conf

DOI

10.1109/CIACS.2014.6861327

Filename

6861327