Novel configurable logic block architecture exploiting controllable-polarity transistors

Controllable-polarity transistors exhibit a device-level configurability. Indeed, they can be dynamically configured between n-type and p-type. Such property can be exploited in Field Programmable Gate Arrays (FPGAs) to replace traditional Look-Up Tables (LUTs) by more powerful configurable units. We report here on a new FPGA logic block architecture, called MCluster, that takes a direct advantage of configurable transistors. The performance of the approach is evaluated and compared to its traditional Complementary Metal-Oxide-Semiconductor (CMOS) counterpart at 22-nm technology node. We note an average saving of 64% in area×delay×power product.