A Just-in-Time Compiler for a Reconfigurable Testing Platform

Author

El-Kadri, Mohammad ; Groza, Voiçu ; Abielmona, Rami ; Assaf, Mansour

Author_Institution

Sch. of Inf. Technol. & Eng., Ottawa Univ., Ont.

fYear

2006

fDate

24-27 April 2006

Firstpage

628

Lastpage

632

Abstract

With the evolution of reconfigurable architectures emerged the field of run-time reconfiguration (RTR). This paper presents a just-in-time (JIT) compiler for a reconfigurable testing platform making use of the ISCAS 85 combinational benchmark circuits making use of the stuck-at fault model. The compiler is discussed in detail as well as some preliminary results of the platform running different circuit under test (CUTs). This paper is part of the ERACE (Groza et al., 2004) project at the GEMS research lab

Keywords

automatic test pattern generation; fault simulation; field programmable gate arrays; just-in-time; program compilers; reconfigurable architectures; ERACE project; FPGA; GEMS research lab; circuit under test; embedded RTOS-MicroBlaze Softcore Processor; embedded cores-based systems; just-in-time compiler; reconfigurable architectures; reconfigurable testing platform; run-time reconfiguration; stuck-at fault model; test pattern generator; Benchmark testing; Central Processing Unit; Circuit faults; Circuit testing; Coprocessors; Fault detection; Field programmable gate arrays; Hardware; System testing; Test pattern generators; Embedded RTOS/MicroBlaze Softcore Processor; FPGA; circuit under test (CUT); embedded cores-based systems; test pattern generator (TPG);

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference, 2006. IMTC 2006. Proceedings of the IEEE

Conference_Location

Sorrento

ISSN

1091-5281

Print_ISBN

0-7803-9359-7

Electronic_ISBN

1091-5281

Type

conf

DOI

10.1109/IMTC.2006.328637

Filename

4124402