A Reconfigurable Multi-Mode Architecture for Reed-Solomon Codec

In order to save the hardware cost and reduce the power consuming in Reed-Solomon codec, a reconfigurable multi-mode codec is presented, which provides support to encoder and decoder. The reconfigurable calculation module (RCM) in the codec can be reconfigured to perform as a linear feedback shift register (LFSR), syndrome generator and Chien´s search algorithm calculator and can handle variable error correction capability (0 <; t ≤ 8). The design, written in hardware description language (HDL), was realized by using Altera´s FPGA. The result proves that the codec could operation at a max frequency of 90 MHz, and the total logic element count is 2887. This design is suitable for systems such as cable modem and digital video broadcasting (DVB).