A coding-based configurable and asymmetrical redundancy scheme for 3-D interconnects

Redundant through-silicon-vias (TSV) are essential to cope with the relatively low yield of current 3-D technologies. In this work we propose a redundant approach for 3-D integrated circuits based on coding. In contrast to conventional redundancy schemes, our approach does not require the BISR to configure both the transmitter and receiver; thus, it reduces the configuration overhead considerably. Moreover, it combines intrinsically yield enhancement, error correction and possibly low-power coding. Exhaustive experimental results at the gate-level in a commercial 65nm technology confirm the efficiency of the approach.