Title :
Fault modelling and collapsing in MOS circuits
Author_Institution :
Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
Abstract :
The author presents a comprehensive fault model for MOS circuits described at mixed gate and switch levels. Fault equivalence rules are introduced based on a careful consideration of distinctive aspects of these circuits, such as strength of devices and transistor fanout relations. A fault collapsing algorithm is given, and it is shown to be efficient both in terms of storage required and CPU time needed. The fault model and collapsing technique were applied to fault generation in the Mozart CAD system
Keywords :
circuit reliability; failure analysis; field effect integrated circuits; integrated logic circuits; logic testing; CPU time needed; MOS circuits; Mozart CAD system; collapsing technique; comprehensive fault model; fault collapsing algorithm; fault generation; gate level; storage required; strength of devices; switch levels; transistor fanout relations; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Logic devices; Logic gates; MOSFETs; Switches; Switching circuits;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo
DOI :
10.1109/ISCAS.1988.15018
