DocumentCode
1881211
Title
A new method for two dimensional symbolic compaction of IC layout
Author
Cheng, Y. ; Fujii, R.
Author_Institution
Sch. of Electr. Eng., Purdue Univ., W. Lafayette, IN, USA
Volume
1
fYear
1989
fDate
3-6 Jan 1989
Firstpage
14
Abstract
A method for two-dimensional IC symbolic layout compaction is presented. Distances between the layout elements and the selected origin are minimized to achieve a compacted layout. Compared to one-dimensional compaction, this algorithm gets better results and its time complexity is of the same order
Keywords
VLSI; circuit layout CAD; IC layout; VLSI; layout elements; time complexity; two dimensional symbolic compaction; Assembly; Compaction; Computational modeling; Data structures; Integrated circuit layout; Joining processes; Minimization; Simulated annealing; Tiles; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
System Sciences, 1989. Vol.I: Architecture Track, Proceedings of the Twenty-Second Annual Hawaii International Conference on
Conference_Location
Kailua-Kona, HI
Print_ISBN
0-8186-1911-2
Type
conf
DOI
10.1109/HICSS.1989.47138
Filename
47138
Link To Document