Generating valid tests for static CMOS-circuits based on a delay model

An approach to automatic test-pattern generation for static CMOS combinational circuits is described. Physical failures that occur in these devices will cause some conditions that are hard to test. Due to high impedance states, CMOS stuck-open faults require test pattern pairs (I, T) where I denotes an initialization pattern and pattern T performs the test. Test pairs of this type must be determined properly taking into account the possibilities of a charge loss during the transition from I to T. A novel algorithm is presented that finds such test pairs that are valid, even in the presence of arbitrary circuit delays. Based on a delay model a method was developed to determine test pairs even for such cases when other algorithms will fail. A fast search strategy is applied for efficient test-pattern generation.<>