Title :
A methodology for quick turn-around of high performance DSP ASICS
Author :
Ang, Peng H. ; Ruetz, Peter A.
Author_Institution :
LSI Logic Corp., Menlo Park, CA, USA
Abstract :
An approach that has been successfully in the design of a family of high-performance digital signal processors is described. It offers the advantage of a short design cycle without sacrificing performance. The method relies on the availability of a well-characterized standard cell library, an accurate gate-level simulator, a behavioral simulator for architectural evaluations, and module generators for generic digital signal processing operators such as multipliers and adders. The method has the flexibility of being able to retarget the logic description into either an array-based, cell-based, or even full-custom physical implementation
Keywords :
application specific integrated circuits; digital signal processing chips; DSP ASICS; adders; architectural evaluations; behavioral simulator; digital signal processors; gate-level simulator; logic description; module generators; multipliers; standard cell library; Adders; Application specific integrated circuits; Design methodology; Digital signal processing; Large scale integration; Logic arrays; Logic design; Nonlinear filters; Signal design; Signal processing;
Conference_Titel :
System Sciences, 1989. Vol.I: Architecture Track, Proceedings of the Twenty-Second Annual Hawaii International Conference on
Conference_Location :
Kailua-Kona, HI
Print_ISBN :
0-8186-1911-2
DOI :
10.1109/HICSS.1989.47140
