A methodology for quick turn-around of high performance DSP ASICS

An approach that has been successfully in the design of a family of high-performance digital signal processors is described. It offers the advantage of a short design cycle without sacrificing performance. The method relies on the availability of a well-characterized standard cell library, an accurate gate-level simulator, a behavioral simulator for architectural evaluations, and module generators for generic digital signal processing operators such as multipliers and adders. The method has the flexibility of being able to retarget the logic description into either an array-based, cell-based, or even full-custom physical implementation