Title :
Latch-up test structures for reliability analysis of a floating well based smart power technology
Author :
Vidal, M. Puig ; Bafleur, M. ; Buxo, J. ; Sarrabayrouse, G.
Author_Institution :
Lab. d´´Autom. et d´´Anal. des Syst., CNRS, Toulouse, France
Abstract :
Self-isolated CMOS double-diffusion MOS (DMOS) technology is a cost effective smart power technology. It is shown that, using a floating well concept as latch-up protection, self-isolated CMOS/DMOS technology can be made cost effective and reliable. The reliability of this concept is demonstrated as far as both static and dynamic latch-up is concerned, as well as with regard to MOS transistor performance
Keywords :
CMOS integrated circuits; circuit reliability; integrated circuit technology; power integrated circuits; MOS transistor performance; double-diffusion MOS; dynamic latch-up; floating well based smart power technology; reliability analysis; self-isolated CMOS/DMOS technology; static latch-up; Birth disorders; CMOS technology; Costs; Integrated circuit reliability; Integrated circuit technology; Isolation technology; MOS devices; Testing; Vehicles; Voltage;
Conference_Titel :
Microelectronic Test Structures, 1993. ICMTS 1993. Proceedings of the 1993 International Conference on
Conference_Location :
Sitges
Print_ISBN :
0-7803-0857-3
DOI :
10.1109/ICMTS.1993.292885
