Title :
An approach to design totally self-checking checker for the 1-out-of-3 code at transistor level
Author :
Tao, D.L. ; Lala, P.K. ; Hartmann, C.R.P.
Author_Institution :
Syracuse Univ., NY, USA
Abstract :
The authors propose a TSC (totally self-checking) checker in MOS technology for 1/3 code based on a set of physical defects. Although it is not possible to design such a checker at the gate level, both analysis and computer simulation show that the proposed checker is a TSC checker for 1/3 code with respect to the given set of faults at the transistor level. Such a checker can be easily incorporated in self-checking design of VLSI chips.<>
Keywords :
VLSI; field effect integrated circuits; integrated circuit testing; logic design; logic testing; 1-out-of-3 code; 1/3 code; MOS technology; computer simulation; design for testability; design method; gate level; self-checking design of VLSI chips; set of physical defects; totally self-checking checker; transistor level; Analytical models; Built-in self-test; Circuit faults; Circuit simulation; Electrical fault detection; Fault detection; Fault tolerant systems; Information science; Logic design; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo, Finland
DOI :
10.1109/ISCAS.1988.15020
