Power lateral DMOS transistor test structures

Author

Hidalgo, S. ; Fernandez, J. ; Godignon, P. ; Rebollo, J. ; Millan, J.

Author_Institution

Centro Nacional de Microelectron., Barcelona, Spain

fYear

1993

fDate

22-25 Mar 1993

Firstpage

33

Lastpage

38

Abstract

The design and the fabrication of LDMOS test structures are discussed. The impact of cell dimensions and epilayer properties on the device characteristics is shown, together with the optimization of V _BR/R_ON trade-off. The influence of device layout, edge device termination and geometrical dimensions are investigated with these test structures. Square, circular, single-finger, multi-finger, and waved gate layouts are considered in the test monitor chip. The fabrication process is a conventional poly-gate double diffusion MOS (DMOS) process based on a double diffusion for the active channel formation. The resurfed LDMOS physical behavior is analyzed by means of 2D simulations. The results obtained are compared with experimental data

Keywords

insulated gate field effect transistors; power transistors; semiconductor device testing; LDMOS test structures; active channel formation; cell dimensions; circular layouts; device characteristics; device layout; edge device termination; epilayer properties; geometrical dimensions; multi-finger layouts; poly-gate double diffusion MOS; power transistors; resurfed LDMOS physical behavior; single-finger layouts; square layouts; waved gate layouts; Breakdown voltage; Design optimization; Doping; Epitaxial layers; Fabrication; Low voltage; MOSFETs; Monitoring; Substrates; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1993. ICMTS 1993. Proceedings of the 1993 International Conference on

Conference_Location

Sitges

Print_ISBN

0-7803-0857-3

Type

conf

DOI

10.1109/ICMTS.1993.292897

Filename

292897