Title :
Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs
Author :
Ando, Yuki ; Shibata, Seiya ; Honda, Shinya ; Takada, Hiroaki ; Tomiyama, Hiroyuki
Author_Institution :
Grad. Sch. of Inf. Sci., Nagoya Univ., Nagoya, Japan
Abstract :
This paper presents an efficient design-space exploration method to identify the Pareto solution for the relation between the execution time and the hardware area. Initially, our method takes a particular system mapping that is surely in the Pareto solution, and then repeats the local search and the update of the Pareto solution until the Pareto solution reaches a steady state. Compared to genetic-algorithm-based methods, we found that our method outputs the Pareto solution with a smaller number of explorations for larger design spaces.
Keywords :
Pareto optimisation; field programmable gate arrays; genetic algorithms; hardware-software codesign; logic design; search problems; FPGA; Pareto solution; SW-HW codesign; fast design-space exploration method; genetic-algorithm-based methods; local search; system mapping; Algorithm design and analysis; Computer architecture; Educational institutions; Embedded systems; Field programmable gate arrays; Space exploration; Transform coding; Design methodology; Design space exploration; Multi-core processor; System-level design;
Conference_Titel :
Field-Programmable Custom Computing Machines (FCCM), 2014 IEEE 22nd Annual International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
978-1-4799-5110-9
DOI :
10.1109/FCCM.2014.70
