Title :
Generic test chip formats for ASIC-oriented semiconductor process development
Author_Institution :
Hewlett-Packard Corp., Palo Alto, CA, USA
Abstract :
A novel approach towards test chip and test structure design is accelerating the introduction of application specific integrated circuit (ASIC)-oriented CMOS process generations. Specialized test chips address quality manufacturability and process integration issues within the proper time frame. Six generic test chip design formats repeat from generation to generation with scaled layout rules
Keywords :
CMOS integrated circuits; application specific integrated circuits; integrated circuit manufacture; integrated circuit testing; quality control; semiconductor process modelling; ASIC-oriented semiconductor process development; CMOS process; generic test chip; process integration; quality manufacturability; scaled layout rules; test chip formats; test structure design; Application specific integrated circuits; Chip scale packaging; Circuit testing; Computer aided manufacturing; Fabrication; Life estimation; Process control; Random access memory; Semiconductor device testing; System testing;
Conference_Titel :
Microelectronic Test Structures, 1993. ICMTS 1993. Proceedings of the 1993 International Conference on
Conference_Location :
Sitges
Print_ISBN :
0-7803-0857-3
DOI :
10.1109/ICMTS.1993.292911
