DocumentCode
1882080
Title
Jitter due to signal history in digital logic circuits and its control strategies
Author
Zukowski, C.A.
fYear
1993
fDate
3-6 May 1993
Firstpage
2114
Lastpage
2117
Keywords
Clocks; Data communication; Driver circuits; History; Logic circuits; Phase locked loops; Pipeline processing; Propagation delay; Throughput; Timing jitter;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
IEEE
Print_ISBN
0-7803-1281-3
Type
conf
Filename
693099
Link To Document