DocumentCode
1882195
Title
Test structure metrology of homogeneous contamination
Author
Parks, H.G. ; Schrimpf, R.D. ; Craigin, R. ; Jones, Ronald ; Resnick, Paul
Author_Institution
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
fYear
1993
fDate
22-25 Mar 1993
Firstpage
207
Lastpage
212
Abstract
Test structures are fabricated with known amounts of iron and copper contamination in the pregate oxide clean of a 1.25-μm CMOS process. Diode and capacitor measurements indicate device degradation in the case of copper, confirming deposition studies indicating that copper deposits from HF solutions. Iron contaminated wafers show no contamination-related device effects, in support of theoretical predictions and of deposition studies indicating that iron does not deposit from HF solutions. The importance and potential usefulness of test structures as homogeneous contamination monitors is illustrated though device modeling of the contamination effects
Keywords
CMOS integrated circuits; integrated circuit testing; semiconductor process modelling; surface treatment; 1.25 micron; CMOS process; Cu; Fe; capacitor measurements; contamination-related device effects; deposition studies; device degradation; device modeling; diode measurements; homogeneous contamination; pregate oxide clean; test structures; CMOS process; Capacitors; Contamination; Copper; Diodes; Hafnium; Iron; Metrology; Pollution measurement; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 1993. ICMTS 1993. Proceedings of the 1993 International Conference on
Conference_Location
Sitges
Print_ISBN
0-7803-0857-3
Type
conf
DOI
10.1109/ICMTS.1993.292919
Filename
292919
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