Title :
Speed optimization of edge-triggered nine-transistor D-flip-flops for gigahertz single-phase clocks
Author_Institution :
Swiss Federal Institute of Technology
Keywords :
CMOS technology; Capacitance; Clocks; Digital circuits; Driver circuits; Humans; Integrated circuit technology; Laboratories; Performance analysis; Voltage;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
IEEE
Print_ISBN :
0-7803-1281-3
