Title :
Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices
Author :
Katoh, Kentaroh ; Ito, Hideo
Author_Institution :
Graduate Sch. of Sci. & Technol., Chiba Univ.
Abstract :
This paper proposes a BIST (built-in self test) method for testing the PEs (processing elements) of multi-context based dynamically reconfigurable processor. We use flip-flops existing in PEs to constitute the test circuit which has the function of LFSR (linear feedback shift register) and MISR (multiple input signature register) as DFT (design for testability). This method can reduce test execution time while maintaining the high rate of fault coverage. Evaluation of the proposed method examined on DRP-I, a coarse grained dynamically reconfiguration processor developed by NEC electronics in 2002 is presented. The number of test configurations and test execution time can be reduced 59.0% and 89.3% respectively compared to a deterministic test with 4.3% area overhead
Keywords :
built-in self test; design for testability; fault simulation; flip-flops; logic testing; microprocessor chips; reconfigurable architectures; shift registers; built-in self-test; coarse grained dynamically reconfigurable devices; coarse grained dynamically reconfiguration processor; design for testability; fault coverage; flip-flops; linear feedback shift register; multicontext based dynamically reconfigurable processor; multiple input signature register; processing elements; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design for testability; Energy consumption; Feedback circuits; Large scale integration; Linear feedback shift registers; National electric code; BIST(Built-In Self Test); Coarse Grained Dynamically Reconfigurable; DFT; DRP; Devices; PE.;
Conference_Titel :
Test Symposium, 2006. ETS '06. Eleventh IEEE European
Conference_Location :
Southampton
Print_ISBN :
0-7695-2566-0
DOI :
10.1109/ETS.2006.10
