Fault Injection-based Reliability Evaluation of SoPCs

Author

Reorda, M. Sonza ; Sterpone, L. ; Violante, M. ; Portela-Garcia, M. ; Lopez-Ongil, C. ; Entrena, L.

Author_Institution

Dipt. di Automatica e Informatica, Politecnico di Torino

fYear

2006

fDate

21-24 May 2006

Firstpage

75

Lastpage

82

Abstract

Systems-on-programmable-chip (SoPCs) include processors, memories and programmable logic that allow to catch multiple application requirements such as high performance, reconfigurability and low-costs. Due to these characteristics, they are also becoming very attractive for safety-critical applications. However, the issue of assessing the reliability they can provide and debugging the possible safety-related mechanisms they embed is still open. In this paper, we present a new fault-injection approach for evaluating the impact of transient faults in SoPCs. Fault-injection experiments are reported on a case study consisting of a Web server implemented on a Xilinx Virtex-II FPGA embedding a PowerPC 405 and running the whole TCP/IP stack

Keywords

fault simulation; field programmable gate arrays; integrated circuit reliability; logic testing; microprocessor chips; programmable circuits; system-on-chip; PowerPC 405; TCP/IP stack; Web server; Xilinx Virtex-II FPGA; fault injection-based reliability evaluation; memories; processors; programmable logic; safety-critical applications; safety-related mechanisms; systems-on-programmable-chip; transient faults; Aerospace electronics; Automatic logic units; Costs; Debugging; Field programmable gate arrays; Logic testing; Memory management; Microprocessors; Programmable logic arrays; Programmable logic devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2006. ETS '06. Eleventh IEEE European

Conference_Location

Southampton

Print_ISBN

0-7695-2566-0

Type

conf

DOI

10.1109/ETS.2006.24

Filename

1628157