Retention-Aware Test Scheduling for BISTed Embedded SRAMs

In this paper we address the test scheduling problem for built-in self-tested (BISTed) embedded SRAMs (e-SRAMs) when data retention faults (DRFs) are considered. The proposed test scheduling algorithm utilizes the "retention-aware" test power model (Wang et al., 2005) to minimize the total testing time of e-SRAMs while not violating given power constraints. Without losing generality, we consider both cases where the pause time for data retention faults is fixed and cases where it can be varied. Experimental results show that the "retention-aware" test scheduling algorithm can reduce the testing time of e-SRAMs up to more than 98 percent at the computational time within a second