A Flexible and Scaleable Methodology for Testing High Speed Source Synchronous Interfaces on ATE with Multiple Fixed Phase Capture and Compare

The increasing bandwidth requirements of mainstream computing and consumer products, as well as the inefficiency of embedded clock interfaces in terms of latency, protocol overhead and power requirements have caused the traditional source synchronous interfaces like DRAM memory to break the gigabit range. Above 1Gbps dynamic effects like drift and jitter might become critical for traditional test approaches. At the same time the usage of dedicated source synchronous ATE HW solutions is challenged by the economic pressure and the flexibility requirements. This paper describes a new test methodology based on traditional ATE architecture which can deliver both, detailed characterization results or just a pass/fail decision for a parametric validation in production - depending on the actual test requirement