• DocumentCode
    1882625
  • Title

    NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers

  • Author

    Lizhong Chen ; Pinkston, T.M.

  • Author_Institution
    Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California Los Angeles, Los Angeles, CA, USA
  • fYear
    2012
  • fDate
    1-5 Dec. 2012
  • Firstpage
    270
  • Lastpage
    281
  • Abstract
    While power-gating is a promising technique to mitigate the increasing static power of a chip, a fundamental requirement is for the idle periods to be sufficiently long to compensate for the power-gating and performance overhead. On-chip routers are potentially good targets for power optimizations, but few works have explored effective ways of power-gating them due to the intrinsic dependence between the node and router -- any packet (sent, received or forwarded) must wakeup the router before being transferred, thus breaking the potentially long idle period into fragmented intervals. Simulation shows that directly applying conventional power-gating techniques would cause frequent state-transitions and significant energy and performance overhead. In this paper, we propose NoRD (Node-Router Decoupling), a novel power-aware on-chip network approach that provides for power-gating bypass to decouple the node´s ability for transferring packets from the powered-on/off status of the associated router, thereby maximizing the length of router idle periods. Full system evaluation using PARSEC benchmarks shows that the proposed approach can substantially reduce the number of state-transitions, completely hide wakeup latency from the critical path of packet transport and eliminate node-network disconnection problems. Compared to an optimized conventional power-gating technique applied to on-chip routers, NoRD can further reduce the router static energy by 29.9% and improve the average packet latency by 26.3%, with only 3% additional area overhead.
  • Keywords
    network routing; network-on-chip; NoRD; critical path; effective power-gating; fragmented intervals; intrinsic dependence; node ability; node-network disconnection problem elimination; node-router decoupling; on-chip routers; packet transport; performance overhead; power optimizations; power-aware on-chip network approach; powered-on-off status; router idle periods; state-transitions; static energy reduction; wakeup latency;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microarchitecture (MICRO), 2012 45th Annual IEEE/ACM International Symposium on
  • Conference_Location
    Vancouver, BC
  • ISSN
    1072-4451
  • Print_ISBN
    978-1-4673-4819-5
  • Type

    conf

  • DOI
    10.1109/MICRO.2012.33
  • Filename
    6493626