Title :
On-Chip Time Measurement Architecture with Femtosecond Timing Resolution
Author :
Collins, Matthew ; Al-Hashimi, Bashir M.
Author_Institution :
Sch. of Electron. & Comput. Sci., Southampton Univ.
Abstract :
This paper presents a new on-chip time measurement architecture which is based on the time-to-digital conversion (TDC) method that is capable of achieving a timing resolution of tens of femtoseconds without the use of external automatic test equipment (ATE). This is the highest temporal resolution that has been reported to-date and is achieved by the use of the homodyne technique. The proposed architecture has been designed using a 0.12mum CMOS process and simulation results based on foundry transistor models indicates that it is possible to achieve a timing resolution of 40 fs. The time measurement architecture is standalone and occupies a small silicon area, 150mum by 180mum, making it attractive for high resolution on-chip time measurement
Keywords :
CMOS integrated circuits; analogue-digital conversion; automatic test equipment; integrated circuit design; time measurement; 0.12 micron; 150 micron; 180 micron; CMOS process; automatic test equipment; femtosecond timing resolution; foundry transistor models; homodyne technique; on-chip time measurement architecture; temporal resolution; time-to-digital conversion; Automatic test equipment; CMOS process; Computer architecture; Oscillators; Semiconductor device modeling; Testing; Time measurement; Timing; Ultrafast electronics; Very large scale integration;
Conference_Titel :
Test Symposium, 2006. ETS '06. Eleventh IEEE European
Conference_Location :
Southampton
Print_ISBN :
0-7695-2566-0
DOI :
10.1109/ETS.2006.36
