Reducing Sampling Clock Jitter to Improve SNR Measurement of A/D Converters in Production Test

Random jitter, present in the clock that is used for sampling the input signal, applied to the A/D converter results in noise that is added to the output of the device. For high-resolution A/D converters (low quantization noise), a very low-jitter clock is needed to measure accurate signal-to-noise ratio. Low jitter constraints on the clock signal increases with the test stimulus frequency. This paper implements a board-level, low-cost, phase-locked-loop (PLL) based approach to reduce the jitter present in the sampling clock provided by a low-cost tester. A small loop bandwidth PLL, a low-noise voltage controlled crystal oscillator (VCXO) and a low-cost (higher jitter) reference clock are used to synthesize a low-jitter clock. The proposed approach was simulated using Simulink and validated using hardware measurements. The results show significant improvement in RMS jitter that improves the SNR measurement of the A/D converter by 3dB