A High Efficient Common IPC for LTE Layer1 Multi-core DSP/SoC System

Multi-core digital signal processor (DSP) and system on chip (SoC) are widely used in LTE baseband these years. A companion paper (Hao Xiang et at., 2013) [1] presented a kind of 3 layers multi-core DSP/SoC software architecture, and mentioned the common IPC is the key for this flexible architecture. This common IPC is detailed in this paper. LTE system has hundreds of configurations from different antenna numbers, bandwidth and Downlink Uplink ratios combinations. The task-core mapping should always be updated according to different configuration scenario. However, this update will seriously impact the software architecture, if the task-core mapping is visible to the architecture. This paper presents a shared memory based IPC. It automatically adapts to the different task-core mapping scenarios, provides a common and transparent IPC channel to the upper layers. Based on this common IPC, each task can be flexibly mapped to any core dynamically. And this dynamic mapping is transparent to the upper layers, so it hasn´t impact on the software architecture any more. This paper makes several contributions to the common IPC development. The first one is the shared memory self-healing circular buffer design. This shared memory based design supports zero-copy, so as to improve the IPC efficiency. This design also supports self-check and self-recovery, so as to achieve the self-healing reliability. The second one is the inter-core N senders - 1 receiver IPC channel design. The third one is the IPC commonizing and optimization for multi-core system. Our evaluation shows the advantages of this common IPC. 1) It is common and transparent to upper layers, so it supports the flexibly task-core mapping. 2) It is a high efficient IPC. After the optimization, in the 256 bytes message inter-core IPC case, it is 4.5 times faster than the same IPC in SmartOS.