Title :
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
Author :
Amory, Alexandre M. ; Goossens, Kees ; Marinissen, Erik Jan ; Lubaszewski, Marcelo ; Moraes, Fernando
Author_Institution :
Instituto de Informatica, Fed. Univ. of RGS, Porto Alegre
Abstract :
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. We demonstrate that these interconnects abstract the interconnect details and provide predictability in the data transfer, which are desirable not only for the functional domain but also for the test application. The proposed wrapper is implemented in VHDL and integrated to the Ethereal NoC. The results show the impact of bandwidth in the core test time. The wrapper area and core test time are compared with a wrapper design for dedicated TAM
Keywords :
integrated circuit design; integrated circuit interconnections; integrated circuit testing; system-on-chip; Ethereal NoC; VHDL; interconnect wrapper design; networks-on-chip; on-chip protocol; test access mechanism; Bandwidth; Cryptography; Delay; Integrated circuit testing; Laboratories; Manufacturing; Network-on-a-chip; Protocols; Scalability; System testing;
Conference_Titel :
Test Symposium, 2006. ETS '06. Eleventh IEEE European
Conference_Location :
Southampton
Print_ISBN :
0-7695-2566-0
DOI :
10.1109/ETS.2006.48
