FPGA Design and Implementation of MIMO Decoder for 1 Gbps Wireless LAN

Author

Ruyue Dong ; Guixia Kang ; Xiaoshuang Liu ; Yuncheng Liu

Author_Institution

Key Lab. of Universal Wireless, Beijing Univ. of Posts &Telecommun., Beijing, China

fYear

2014

fDate

13-15 Oct. 2014

Firstpage

458

Lastpage

463

Abstract

This paper presents a high throughput pipeline decoder architecture for multiple input multiple output (MIMO) with good performance and its field programmable gate array (FPGA) implementation. This enhanced pipeline decoder architecture can handle large amounts of data and is suitable for very high throughput system. Based on the proposed architecture, the pipeline decoder architecture has been implemented on Xilinx Virtex5 SX95T FPGA. The results show that when signal-to-noise ratio (SNR) is higher than 25dB, the architecture can achieve a throughput up to 1.16Gbps with bit error rate (BER) lower than 10^-6.

Keywords

MIMO communication; decoding; field programmable gate arrays; wireless LAN; BER; FPGA implementation; MIMO; Xilinx Virtex5 SX95T FPGA; bit error rate; bit rate 1.16 Gbit/s; field programmable gate array implementation; high throughput pipeline decoder architecture; multiple input multiple output; signal-to-noise ratio; wireless LAN; Algorithm design and analysis; Complexity theory; Decoding; MIMO; Pipelines; Receiving antennas; Throughput; FPGA implementation; MIMO decoder; pipeline architecture; wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Cyber-Enabled Distributed Computing and Knowledge Discovery (CyberC), 2014 International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4799-6235-8

Type

conf

DOI

10.1109/CyberC.2014.85

Filename

6984350