A 45-Mbits/sec. VLSI Viterbi decoder for digital video applications

Author

Edwards, Gwyn

Author_Institution

Stanford Telecom Inc., Sunnyvale, CA, USA

fYear

1993

fDate

16-17 Jun 1993

Firstpage

127

Lastpage

130

Abstract

The author describes the unique architecture and feature set incorporated into the STEL-2060 Viterbi Decoder, a VLSI device designed by Standford Telecom. This device was designed primarily for direct broadcasting by satellite (DBS) services and operates up to 45 Mb/s. The STEL-2060 uses industry standard, constraint length 7, polynomials and incorporates depuncturing circuitry to allow it to be used with punctured codes up to rate 7/8, as well as standard rate 1/2 coding

Keywords

CMOS integrated circuits; VLSI; codecs; decoding; digital signal processing chips; direct broadcasting by satellite; parallel architectures; video equipment; 45 Mbit/s; 45-Mbits/s VLSI Viterbi decoder; DBS; STEL-2060 Viterbi decoder; Standford Telecom; architecture; constraint length 7 polynomials; depuncturing circuitry; digital video applications; direct broadcast satellite; feature set; punctured codes; Application specific integrated circuits; Code standards; Decoding; Digital communication; Forward error correction; Satellite broadcasting; Signal design; Telecommunications; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Telesystems Conference, 1993. 'Commercial Applications and Dual-Use Technology', Conference Proceedings., National

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-1325-9

Type

conf

DOI

10.1109/NTC.1993.292997

Filename

292997