Title :
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction
Author :
Raychowdhury, Arijit ; Geuskens, Bibiche ; Kulkarni, Jitendra ; Tschanz, James ; Bowman, Keith ; Karnik, T. ; Shih-Lien Lu ; De, Vivek ; Khellah, Muhammad M.
Author_Institution :
Intel, Hillsboro, OR, USA
Abstract :
A 16 KB 8T register-file macro in a 45 nm CMOS process uses on-die PVT-adaptive boosting of read- and write-wordline for minimizing VMN while reducing boosting overhead for maximum power benefit. Measurements of 1 MB 8T arrays in a single-VCC ¿mP core indicate 6 to 27% lower power for arrays access variations of 10% (75 pF) to 30% (1 nF).
Keywords :
CMOS memory circuits; SRAM chips; 8T SRAM power reduction; CMOS process; PVT; aging adaptive wordline boosting; read-and write-wordline; register-file macro; size 45 nm; Aging; Boosting; Circuits; Clocks; Frequency; Low voltage; MOS devices; Rails; Random access memory; Temperature sensors;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433815
