DocumentCode
1883466
Title
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction
Author
Raychowdhury, Arijit ; Geuskens, Bibiche ; Kulkarni, Jitendra ; Tschanz, James ; Bowman, Keith ; Karnik, T. ; Shih-Lien Lu ; De, Vivek ; Khellah, Muhammad M.
Author_Institution
Intel, Hillsboro, OR, USA
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
352
Lastpage
353
Abstract
A 16 KB 8T register-file macro in a 45 nm CMOS process uses on-die PVT-adaptive boosting of read- and write-wordline for minimizing VMN while reducing boosting overhead for maximum power benefit. Measurements of 1 MB 8T arrays in a single-VCC ¿mP core indicate 6 to 27% lower power for arrays access variations of 10% (75 pF) to 30% (1 nF).
Keywords
CMOS memory circuits; SRAM chips; 8T SRAM power reduction; CMOS process; PVT; aging adaptive wordline boosting; read-and write-wordline; register-file macro; size 45 nm; Aging; Boosting; Circuits; Clocks; Frequency; Low voltage; MOS devices; Rails; Random access memory; Temperature sensors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5433815
Filename
5433815
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