Video chip set for data rate compression by filtering and DPCM coding

Author

Zehner, B. ; Mattausch, H.J. ; Matthiesen, F. ; Schoebinger, M. ; Tielert, R. ; Klar, H. ; Moehrmann, K.H.

Author_Institution

Siemens AG, Munich, West Germany

fYear

1988

fDate

7-9 June 1988

Firstpage

697

Abstract

Low-cost transmission of digital color TV signals for ISDN needs a data reduction to reduce the required channel bandwidth. A CMOS chip set performing a data rate compression from 140 Mb/s to 34 Mb/s is presented. It consists of a digital filter of sixth order switchable to horizontal or vertical filtering, an adjustable delay line, and a DPCM codec with a two-dimensional prediction algorithm and an adaptive quantizer characteristic. A set of experimental chips has been realized to demonstrate the feasibility of compact low-cost system components and to explore the potential of advanced CMOS technologies. Fully functional first silicon in 1.5- mu m CMOS technology was obtained. The achieved performance data guarantee correct function even under worst-case conditions.<>

Keywords

CMOS integrated circuits; ISDN; bandwidth compression; codes; colour television; data compression; digital communication systems; digital filters; picture processing; pulse-code modulation; 1.5 micron; 140 to 34 Mbit/s; ADPCM video chip set; CMOS chip set; DPCM codec; DPCM coding; ISDN; adaptive quantizer characteristic; adjustable delay line; bandwidth reduction; data rate compression; data reduction; digital filter; experimental chips; feasibility study; filtering; low-cost system components; transmission of digital color TV signals; two-dimensional prediction algorithm; worst-case conditions; Adaptive filters; Bandwidth; CMOS technology; Codecs; Delay lines; Digital filters; Filtering; ISDN; TV; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo, Finland

Type

conf

DOI

10.1109/ISCAS.1988.15021

Filename

15021