Title :
A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias
Author :
Nii, Koji ; Yabuuchi, M. ; Tsukamoto, Yuya ; Hirano, Yoshikuni ; Iwamatsu, Takanori ; Kihara, Yuki
Author_Institution :
Renesas Technol., Kodaira, Japan
Abstract :
We present a 0.5 V 6T SRAM fabricated in a 90 nm PD-SOI technology with asymmetric MOSFET to improve the read and write margin. The design also uses a forward-body-bias technique in the bit-cell and peripheral circuits. The measured minimum operating voltage of the SRAM is 0.45 V at 25°C, which is 100 mV lower than conventional SRAM. The access time is 6.8 ns at 0.5 V.
Keywords :
MOSFET; SRAM chips; silicon-on-insulator; PD-SOI SRAM; Si; asymmetric MOSFET; bit-cell circuit; enhanced read stability; forward body bias; frequency 100 MHz; peripheral circuit; size 90 nm; temperature 25 C; time 6.8 ns; voltage 0.45 V; voltage 0.5 V; write margin; CMOS technology; Capacitance; Circuit testing; Degradation; Doping; MOSFET circuits; Random access memory; Robustness; Stability; Voltage;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433817
