DocumentCode :
1883561
Title :
A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS
Author :
Qazi, M. ; Stawiasz, Kevin ; Chang, Ly-Yu ; Chandrakasan, Anantha
Author_Institution :
Massachusetts Inst. of Technol., Cambridge, MA, USA
fYear :
2010
fDate :
7-11 Feb. 2010
Firstpage :
350
Lastpage :
351
Abstract :
An 8T SRAM fabricated in 45 nm SOI CMOS exhibits voltage scalable operation from 1.2 V down to 0.57 V with access times from 400 ps to 3.4 ns. Timing variation and the challenge of low-voltage operation are addressed with an AC-coupled sense amplifier. An area efficient data path is achieved with a regenerative global-bitline scheme. Finally, a data-retention-voltage sensor is developed to predict the mismatch-limited minimum-standby voltage without corrupting the content of the memory.
Keywords :
CMOS digital integrated circuits; SRAM chips; amplifiers; intelligent sensors; silicon-on-insulator; AC-coupled sense amplifier; SOI CMOS; SRAM; embedded data-retention-voltage sensor; low-voltage operation; mismatch-limited minimum-standby voltage; regenerative global-bitline scheme; size 45 nm; storage capacity 512 Kbit; time 400 ps to 3.4 ns; voltage 1.2 V to 0.57 V; CMOS process; Circuit testing; Equations; MOS capacitors; MOS devices; Random access memory; Sensor phenomena and characterization; Temperature sensors; Threshold voltage; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
978-1-4244-6033-5
Type :
conf
DOI :
10.1109/ISSCC.2010.5433818
Filename :
5433818
Link To Document :
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