Implementation of the Digital Logic for Reading-Out a 16Ã\x9716 Pixel X-Ray Detector Array

Author

Ferragina, V. ; Malcovati, P. ; Ratti, N. ; Cappelluti, I. ; Bertuccio, G.

Author_Institution

Dept. of Electron., Pavia Univ.

fYear

2006

fDate

24-27 April 2006

Firstpage

1263

Lastpage

1267

Abstract

In this paper, we propose the digital logic required for reading-out a 16times16 array of X-ray detectors. The proposed readout strategy allows us to handle an event rate as large as 106 event/s over the whole array and 104 event/s over a single row of the array. The digital logic is embedded in an integrated circuit to be bump-bonded on top of the detector, which includes also the front-end electronics required for processing the sensor output signals and the A/D converter. This work was carried-out in the framework of an ESA research activity

Keywords

X-ray detection; application specific integrated circuits; array signal processing; digital readout; integrated logic circuits; A/D converter; ESA research activity; X-ray detector array; application specific integrated circuit; bump-bonded integrated circuit; digital logic; embedded circuit; front-end electronics; readout circuit; readout strategy; sensor output signal processing; Application specific integrated circuits; Extraterrestrial measurements; Instrumentation and measurement; Logic arrays; Logic circuits; Sensor arrays; Signal processing; Space technology; Spectroscopy; X-ray detectors; Application Specific Integrated Circuit; Readout Circuit; X-Ray Detector;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference, 2006. IMTC 2006. Proceedings of the IEEE

Conference_Location

Sorrento

ISSN

1091-5281

Print_ISBN

0-7803-9359-7

Electronic_ISBN

1091-5281

Type

conf

DOI

10.1109/IMTC.2006.328491

Filename

4124545