Calculation of voltage drops in the vias of a multichip package

A methodology for calculation of the voltage drops in the vias of a multichip package is presented. The vias are treated as lumped-circuit elements, and the excess capacitance and inductance of the vias are not considered. Numerical techniques were employed to determine the voltage and current waveforms of the signal path between two chips. After the current waveforms for the vias were determined, the voltage drop in ground was obtained by multiplying the current by the internal partial impedance. It was found that the peak noise is very small (in the range of 0.0005 V for a parallel-terminated line) for an input of 1 V due to the utilization of multiple power and ground vias in the design considered. it is point out that the location of the vias (relative to the drivers) has to be carefully chosen when the peak voltage drops are to be minimized