Title :
A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS
Author :
Fukuda, Kenji ; Yamashita, Hiromasa ; Ono, Goichi ; Nemoto, R. ; Suzuki, Einoshin ; Takemoto, T. ; Yuki, F. ; Saito, Takashi
Author_Institution :
Hitachi, Kokubunji, Japan
Abstract :
This paper presents a 12.3 mW 12.5 Gb/s complete transceiver in a 65 nm standard digital CMOS process. The chip includes a CDR, MUX/DEMUX, and global clock distribution network. A number of low-power design techniques are described that allow a power efficiency of 0.98 mW/(Gb/s).
Keywords :
CMOS digital integrated circuits; clock and data recovery circuits; clock distribution networks; transceivers; CDR; MUX/DEMUX; clock and data recovery circuits; digital CMOS process; global clock distribution network; power 12.3 mW; size 65 nm; transceiver; Clocks; Delay effects; Driver circuits; Logic; Phase detection; Phase locked loops; Pulse circuits; Testing; Transceivers; Voltage;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433824
