A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS

Author

Balamurugan, Ganesh ; O´Mahony, F. ; Mansuri, Mozhgan ; Jaussi, J.E. ; Kennedy, J.T. ; Casper, Bryan

Author_Institution

Intel, Hillsboro, OR, USA

fYear

2010

fDate

7-11 Feb. 2010

Firstpage

372

Lastpage

373

Abstract

A reconfigurable transceiver capable of adapting its signaling mode to the I/O channel is implemented in 45nm CMOS. When configured for single-ended 2/3/4-PAM, it enables 5-to-25Gb/s signaling over on-package interconnect while dissipating 1.6-to-2.6mW/(Gb/s). Over a backplane channel, a differential source series-terminated signaling configuration with TX pre-emphasis and 1-tap DFE allows 10Gb/s signaling with 3.8mW/(Gb/s) power efficiency.

Keywords

CMOS integrated circuits; integrated circuit interconnections; integrated circuit packaging; pulse amplitude modulation; transceivers; CMOS; I/O channel; TX pre-emphasis; backplane channel; bit rate 5 Gbit/s to 25 Gbit/s; differential source series-terminated signaling configuration; on-package interconnect; power 1.6 mW to 3.8 mW; reconfigurable transceiver; signaling mode; single-ended 2/3/4-PAM; size 45 nm; Backplanes; Circuits; Clocks; Degradation; Leg; MOS devices; Packaging; Routing; Transceivers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4244-6033-5

Type

conf

DOI

10.1109/ISSCC.2010.5433826

Filename

5433826