Title :
An 18b 12.5MHz ADC with 93dB SNR
Author :
Hurrell, Christopher Peter ; Lyden, Colin ; Laing, D. ; Hummerston, Derek ; Vickery, M.
Author_Institution :
Analog Devices, Newbury, UK
Abstract :
This paper describes an 18b 12.5 MHz ADC that uses a pipeline of 2 successive-approximation ADCs. Both ADCs, one before and one after a closed loop residue amplifier, determine 2 bits plus one redundant bit per bit trial. The converter core consumes 105 mW and achieves a dynamic range of 93 dB. The chip is implemented in a 0.25 ¿m/0.5 ¿m CMOS process and occupies 6 mm2.
Keywords :
amplifiers; analogue-digital conversion; SNR; analogue-digital conversion; closed loop residue amplifier; converter core; frequency 12.5 MHz; power 105 mW; signal to noise ratio; size 0.25 mum; size 0.5 mum; successive-approximation ADC; word length 18 bit; Adders; Calibration; Capacitance; Capacitors; Dynamic range; Feedback; Sampling methods; Switches; Testing; Voltage;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433829
